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Content Provider | IET Digital Library |
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Author | Ravezzi, L. |
Abstract | A duty cycle detector based on time-to-digital conversion is presented. It combines the advantages of analogue (high accuracy and simplicity) and digital (digital output) duty cycle correctors in a simple and straightforward topology. Two identical circuits detect the high and low phases of the input clock and deliver two digital words. These two words are then sufficient to accurately estimate the input duty cycle. By using the same topology for both circuits, accuracy is affected only by mismatches between them. Designed in a bulk 28nm CMOS technology the proposed duty cycle detector achieves a maximum linearity error of 4% and a resolution of 0.5% over corners and an input duty cycle range of [20, 80]%. |
Starting Page | 247 |
Ending Page | 248 |
Page Count | 2 |
ISSN | 00135194 |
Volume Number | 49 |
e-ISSN | 1350911X |
Issue Number | Issue 4, Feb (2013) |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/49/4 |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2012.4276 |
Journal | Electronics Letters |
Access Restriction | Open |
Rights Holder | © The Institution of Engineering and Technology |
Subject Keyword | A/D And D/A Convertor Analogue-digital Duty Cycle Corrector Bulk CMOS Technology Circuit Topology CMOS Integrated Circuit Demodulator Detector Circuit Digital Word Delivery Discriminators And Mixers Duty-cycle Detector High Phase Input Clock Circuit Detection Input Duty Cycle Estimation Low Phase Input Clock Detection Maximum Linearity Error Modulator Network Topology Size 28 Nm Time-digital Conversion Time-to-digital Conversion |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering |
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