NDLI: Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Content Provider	IET Digital Library
Author	Gu, M. Wang, X. Li, W. Aquilino, M. Peng, J. Wang, H. Jaeger, D. Tabakman, K. Carter, R. Hu, O. Ma, W. Joshi, M. Lee, L.
Abstract	Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable low-power and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1–5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.
Starting Page	514
Ending Page	516
Page Count	3
ISSN	00135194
Volume Number	56
e-ISSN	1350911X
Issue Number	Issue 10, May (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/56/10
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2019.3954
Journal	Electronics Letters
Publisher Date	2020-03-03
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Advanced FinFET Technology Deposition Process Dielectric Breakdown Voltage Dielectric Material And Property Dielectric Property FinFET Gate Sidewall Spacer Gate Electrode Hybrid Low-k Spacer Scheme Insulated Gate Field Effect Transistors Integrated FinFET Technology Platform Leakage Current Low-dielectric Constant Material Low-k Dielectric Thin Film Low-k Material Manufacturing Process MOSFET P/NFET Overlap Capacitance Parasitic Capacitance Reduction Photonic Technology Reliability Reliability Characterisation Ring Oscillator Effective Capacitance Semiconductor Device Breakdown Semiconductor Device Reliability Silicon Compound Silicon Oxycarbonnitride SiOCN Size 7.0 Nm Structural Integrity
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability

Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

Simulation of Multiple Gate FinFET Device Gate Capacitance and Performance with Gate Length and Pitch Scaling

Parasitic Capacitance Extraction of 3-D DG-Finfet with Low K Symmetric Spacer Material

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

Controlling fixed trap charge effect in FinFET using heterodielectric BOX

Temperature effect on the reliability of ZrO/sub 2/ gate dielectric deposited directly on silicon

Discussion group summary gate oxide reliability

Unified TDDB model for stacked high-k dielectrics

Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Similar Documents

The effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability

Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

Simulation of Multiple Gate FinFET Device Gate Capacitance and Performance with Gate Length and Pitch Scaling

Parasitic Capacitance Extraction of 3-D DG-Finfet with Low K Symmetric Spacer Material

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

Controlling fixed trap charge effect in FinFET using heterodielectric BOX

Temperature effect on the reliability of ZrO/sub 2/ gate dielectric deposited directly on silicon

Discussion group summary gate oxide reliability

Unified TDDB model for stacked high-k dielectrics

Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction