NDLI: PSJ LDMOS with a VK dielectric layer

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PSJ LDMOS with a VK dielectric layer

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The Journal of Engineering

PSJ LDMOS with a VK dielectric layer

Content Provider	IET Digital Library
Author	Wu, Lijuan Wu, Yiqing Lei, Bing Zhang, Yinyan Huang, Ye Zhu, Lin
Abstract	A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable-k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low-k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance (R on,sp). Furthermore, according to an enhanced dielectric layer field, low-k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm−2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.
Starting Page	600
Ending Page	603
Page Count	4
Volume Number	14
e-ISSN	17500443
Issue Number	Issue 6, May (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/mnl/14/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/mnl.2018.5467
Journal	Micro & Nano Letters
Publisher Date	2019-05-29
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Buried Layer Charge Compensation Charge Compensation Layer Design And Testing Drift Region Length Electric Field Elemental Semiconductor Enhanced Dielectric Layer Field Equivalent Circuit Figure of Merit FOM High Breakdown Voltage Insulated Gate Field Effect Transistors Lateral BV Lateral Doping Technique Low-k Buried Layer Low-k Dielectric Thin Film Low-k Material Low-resistance Channel MOSFET Partial Super Junction Lateral Double-diffused Metal–oxide–semiconductor Field-effect Transistor PSJ SOI LDMOS PSJ VK LDMOS Semiconductor Device Breakdown Semiconductor Device Modelling Semiconductor Doping Silicon Silicon-on-insulator Size 46.5 Mum Substrate-assisted Depletion Effect VK Dielectric Layer Voltage 795.5 V
Content Type	Text
Resource Type	Article

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