NDLI: Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

Content Provider	IET Digital Library
Author	Pradhan, Kumar Prasannajit Sahu, Kumar Prasannajit
Abstract	Asymmetric underlap dual-k spacer hybrid fin field-effect transistor (FinFET) is a novel hybrid device that combines three significant and advanced technologies, i.e. ultra-thin body, three-dimensional (3D) FinFET, and asymmetric spacer engineering on a single silicon on insulator platform. This innovative architecture promises to enhance the device performance as compared with conventional FinFET without increasing the chip area. Recently, high-k dielectric spacer materials are of research interest due to their better electrostatic control and more immune towards short channel effects in nanoscale devices. For the first time, this study introduces an asymmetric high-k dielectric spacer near the source side with optimised length in hybrid FinFET and claims an improvement in device integrity. From extensive 3D device simulation, the authors have determined that the proposed architecture is superior in performance as compared with traditional FinFET.
Starting Page	441
Ending Page	447
Page Count	7
ISSN	1751858X
Volume Number	10
e-ISSN	17518598
Issue Number	Issue 5, Sep (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/10/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2016.0125
Journal	IET Circuits, Devices & Systems
Publisher Date	2016-09-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	3D Device Simulation Asymmetric Spacer Engineering Asymmetric Underlap Dual-k Spacer Bulk Fin Field-effect Transistor Design And Testing Dielectric Material Dielectric Material And Property Electrostatic Control Equivalent Circuit High-k Dielectric Spacer Material Hybrid Fin Field-effect Transistor Insulated Gate Field Effect Transistors MOSFET Nanoscale Device Semiconductor Device Model Semiconductor Device Modelling Short Channel Effect Silicon on Insulator Silicon-on-insulator Ultrathin Body Three-dimensional FinFET
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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Erratum: Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

Effects of fin width on high-κ/metal gate bulk FinFET devices

Evaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual-k spacer FinFETs

Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Symmetric dual gate insulator-based FinFET module and design window for reliable circuits

Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET

Controlling fixed trap charge effect in FinFET using heterodielectric BOX

Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect

High performance Bulk FinFET with bottom spacer

Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

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Erratum: Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

Effects of fin width on high-κ/metal gate bulk FinFET devices

Evaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual-k spacer FinFETs

Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Symmetric dual gate insulator-based FinFET module and design window for reliable circuits

Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET

Controlling fixed trap charge effect in FinFET using heterodielectric BOX

Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect

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Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor