NDLI: Background calibration of bit weights in pipeline ADCs using a counteracting dither technique

Content Provider	IET Digital Library
Author	Sun, Jie Zhou, Yuan Li, Xin
Abstract	A counteracting dither technique is proposed to remedy the bit-weight error issue in pipeline analogue-to-digital converters (ADCs). A capacitor is added to the traditional comparator dither scheme. By switching the added capacitor, the residue swing increment due to comparator dither is counteracted, thereby greatly relaxing the design requirement of the residue amplifier. Behaviour-level simulation results show that the spurious-free-dynamic-range and the signal-to-noise-and-distortion-ratio are improved from 59 and 52.8 dB to 102.7 and 85 dB after calibration in a 14-bit ADC, respectively.
Starting Page	478
Ending Page	480
Page Count	3
ISSN	00135194
Volume Number	56
e-ISSN	1350911X
Issue Number	Issue 10, May (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/56/10
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2020.0006
Journal	Electronics Letters
Publisher Date	2020-02-27
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Amplifiers Analogue-Digital Conversion Background Calibration Behaviour-level Simulation Bit Weights Bit-weight Error Calibration Capacitor Comparators (circuits) Dither Technique Pipeline ADCs Pipeline Analogue-to-digital Converter Residue Amplifier Residue Swing Increment Signal-to-noise-and-distortion-ratio Spurious-free-dynamic-range Traditional Comparator Dither Scheme Word Length 14 Bit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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