NDLI: Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers

Content Provider	IEEE Xplore Digital Library
Author	Abe, S. Miyazawa, Y. Nakajima, Y. Hanajiri, T. Toyabe, T. Sugano, T.
Copyright Year	2009
Description	Author affiliation: Bio-Nano Electronics Research Centre, Toyo University, 2100 Kujirai, Kawagoe, Saitama 350-8585, Japan (Abe, S.; Miyazawa, Y.; Nakajima, Y.; Hanajiri, T.; Toyabe, T.; Sugano, T.)
Abstract	The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) fabricated on a Silicon-On-Insulator (SOI) substrate is effective to suppress Short Channel Effect (SCE), and is one of the most promising electron devices for Very Large Scale Integration (VLSI) circuits for higher speed, higher integration density, and lower power consumption, and it has been already demonstrated that SCE in deep submicron SOI MOSFETs comes from Drain-Induced Barrier Lowering (DIBL) at SOI/Buried OXide (BOX) interface by the author's group. This paper elucidates the roles of permittivity and thickness of BOX layers in suppressing the DIBL in SOI MOSFETs by performing numerical device simulations of SOI MOSFETs with various permittivity and thickness of BOX systematically and by visualizing distribution of dielectric flux lines and current flow lines as well as contour potential lines in MOSFETs.
Starting Page	329
Ending Page	332
File Size	1090908
Page Count	4
File Format	PDF
ISBN	9781424437047
DOI	10.1109/ULIS.2009.4897602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon on insulator technology Energy consumption Circuits Data visualization Very large scale integration Numerical simulation Permittivity Electron devices MOSFETs Thickness control
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in