NDLI: The disposable dot FET: A strained silicon channel on top of removed SiGe

Please wait, while we are loading the content...

EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

2013 14th International Conference on Ultimate Integration on Silicon (ULIS)

2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

Ulis 2011 Ultimate Integration on Silicon

2009 10th International Conference on Ultimate Integration of Silicon

Proceedings of the $10^{th}$ International conference on ULtimate Integration of Silicon

Silicon spintronics

Advanced SOI CMOS transistor technology for high performance microprocessors

Pockets engineering impact on mismatch performance on 45nm MOSFET technologies

Correlation of fin shape fluctuations to FinFET electrical variability and noise margins of 6-T SRAM cells

Efficient simulations of 6σ VT distributions due to Random Discrete Dopants

Mobility extraction of UTB n-MOSFETs down to 0.9 nm SOI thickness

Accurate effective mobility extraction in SOI MOS transistors

Effect of access resistance on apparent mobility reduction in nano-MOSFET

Static and low frequency noise characterization of FinFET devices

A unified density gradient approach to ‘ab-initio’ ionised impurity scattering in 3D MC simulations of nano-CMOS variability

Full-3D real-space treatment of surface roughness in double gate MOSFETs

Exhaustive experimental study of tunnel field effect transistors (TFETs): From materials to architecture

Simulation study of graphene nanoribbon tunneling transistors including edge roughness effects

Computational exploration of novel silicon nanostructures

High performance Schottky barrier MOSFETs on UTB SOI

Interface engineering for the suppression of ambipolar behavior in Schottky-barrier MOSFETs

Characterization of dopant segregated Schottky barrier source/drain contacts

Impact ionization rates for strained SiGe

Ge and III/V devices for advanced CMOS

Interface oxide trap characterisation in germanium-on-insulator 0.12 μm PMOS transistors by drain current noise measurements

Intrinsic cut off frequency of Si and GaAs based Resonant Tunneling Diodes

Spectroscopic detection of (i) intrinsic band edge defects, and (ii) transition metal (TM) and rare earth lanthanide (REL) atom occupied states in elemental and complex oxides: A novel pathway to (i) device reliability and (ii) increased functionality in ULSI CMOS

Rare-earth based alternative gate dielectrics for future integration in MOSFETs

Quantization effects in silicided and metal gate MOSFETs

Performance enhancement of uniaxially-tensile strained Si NW-nFETs fabricated by lateral strain relaxation of SSOI

Basic insight about the strain engineering of n-type FinFETs

Impact of strain on p-DGMOS performance using full-band Monte Carlo simulation

Modeling of piezoresistive coefficients in Si hole inversion layers

Comparison of advanced transport models for nanoscale nMOSFETs

Implementing brain-like systems using nano functional devices

Phenomenological considerations of resistively switching TiO2 in nano crossbar arrays

Scalability of MSD memory effect

A multilayer RRAM nanoarchitecture with resistively switching Ag-doped spin-on glass

Carbon-based thermal stabilization techniques for junction and silicide engineering for high performance CMOS periphery in memory applications

Organic electronics

A comparative study of non-melt laser spike annealing and flash lamp annealing in terms of transistor performance and pattern effects on SOI-CMOSFETs for the 32 nm node and below

Scalability of advanced partially depleted n-MOSFET devices on biaxial strained SOI substrates

Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement

Underlap channel UTBB MOSFETs for low—power analog/RF applications

The disposable dot FET: A strained silicon channel on top of removed SiGe

Integration of laser-annealed junctions in a low-temperature high-k metal-gate MISFET

Discussion of origins of high-density trap states in SIMOX wafers

Impact of TiN metal gate thickness and the HfSiO nitridation on MuGFETs electrical performance

Peculiarities of electrical properties of metal-insulator-semiconductor capacitors based on high-k dielectric stack containing HfTiSiO:N and HfTiO:N films

Impact of sputter deposited TaN and TiN metal gates on ZrO2/Ge and ZrO2/Si high-k dielectric gate stacks

Detection of strain minimization in Hf-based gate dielectrics by X-ray absorption and non-linear optical second harmonic generation spectroscopy

Interfacial and electrical characterization of HfO2 gate dielectric film with a blocking layer of Al2O3

Electrical characteristics of atomic layer deposited aluminium oxide and lanthanum-zirconium oxide high-k Dielectric stacks

A scalable architecture of associative processors employing nano functional devices

A Parzen-window classifier architecture for massively-integrated nanoscale resonant devices

NBTI tolerant 4T double-gate SRAM design

Using charge self-compensation domino full-adder with multiple supply and dual threshold voltage in 45nm technology

High-κ Ta2O5 film for resistive switching memory application

A nano-functional-device-based image feature extraction circuitry with current-balancing feedback

CMOS sensor array for bi-directional communication with electrically active cells

Power and delay estimation for dynamic OR gates with header and footer transistor based on wavelet neural networks

Silicon nanowire pinch-off FET : Basic operation and analytical model

Sample variability and time stability in scaled silicon nanowires

Effective-mass model of surface scattering in locally oxidized Si nanowires

MESFETs on H-terminated polycrystalline diamond

Modeling of Metal-Semiconductor Field-Effect-Transistor on H- terminated polycrystalline diamond

Design considerations for undoped FinFETs based on a 3D compact model for the potential barrier

Compact modeling of quantization effects for cylindrical gate-all-around MOSFETs

Simulation assessment of process options for advanced CMOS devices

Valley splitting in thin silicon films from a two-band k·p model

Investigation of the vertical IMOS-transistor by device simulation

Impact of strain on the performance of high-k/metal replacement gate MOSFETs

Quantum compact model for ultra-narrow body FinFET

Vth-control method in double gate field effect transistor domino circuits

Using low-k oxide for reduction of leakage current in Double Gate Tunnel FET

A novel structure for improvment the Ion/Ioff ratio in nano-scale double gate source-heterojunction-MOS-transistor

Analytical modeling of Negative Bias Temperature Instability in triple gate MOSFETs

Modeling effect of Negative Bias Temperature Instability on potential distribution and degradation of double-gate MOSFETs

Stable, low power and high performance SRAM based on CNFET

A compact physical model for subthreshold current in nanoscale FD/SOI MOSFETs

Nanoscale Ultra Thin Body-Silicon-On-Insulator field effect transistor with step BOX: Self-heating and short channel effects)

Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers

Study of new novel FinFET device with its bodies been connected

A quantum transport approach to the calculation of gate tunnelling current in Nano-scale FD SOI MOSFETs

Improvement of performance of Drain-Source-On-Insulator MOSFETs by using heavily doped-Si region between local BOX regions

An efficient threshold voltage model for ultra thin body double gate/SOI MOSFETs

Silicon Rich Oxide with controlled mean size of silicon nanocrystals by deposition in multilayers

Quantized logic switch implementation through a superconducting transformer

A surface field based model for ultra thin body undoped symmetric DG MOSFETs

2008 9th International Conference on Ultimate Integration of Silicon

The disposable dot FET: A strained silicon channel on top of removed SiGe

Content Provider	IEEE Xplore Digital Library
Author	Gerharz, J. Mussler, G. Moers, J. Rinke, G. Trellenkamp, S. Grutzmacher, D.
Copyright Year	2009
Description	Author affiliation: Institute of Bio- and Nanosystems, IBN1-HN, Forschungszentrum Julich, D-52425, Germany (Gerharz, J.; Mussler, G.; Moers, J.; Rinke, G.; Trellenkamp, S.; Grutzmacher, D.)
Abstract	This paper presents a silicon MOSFET device, which utilizes locally strained silicon layers for high mobility channels. By means of template-assisted self assembly of Ge-islands and Silicon overgrowth a Silicon layer is formed, which is strained on top of the very accurately placed Ge-islands and their near vicinity. The island formation in the seed holes on pre patterned substrates and the intrinsic overlay of the ebeam lithography were investigated. The island size, shape and distribution can be properly controlled up to a grid pitch of 700 nm. The intrinsic overlay of ±10nm can be maintained during device processing, which is due to the symmetry of the markers.
Starting Page	177
Ending Page	180
File Size	8857205
Page Count	4
File Format	PDF
ISBN	9781424437047
DOI	10.1109/ULIS.2009.4897565
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Germanium silicon alloys FETs Silicon germanium
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in