NDLI: The Test Pattern Generation for Digital Integrated Circuits Based on CA-IA-PSO Algorithm

Content Provider	IEEE Xplore Digital Library
Author	Zhang Jiali Zhang Lin Yang Yun Niu Tianlin Zhang Long Xu Xiaodong
Copyright Year	2015
Description	Author affiliation: Air & Missile Defense Coll., Air Force Eng. Univ., Xi'an, China (Zhang Jiali; Zhang Lin; Yang Yun; Niu Tianlin; Zhang Long; Xu Xiaodong)
Abstract	In order to improve the ability to get rid of partial extreme spot and the diversity of population in evolution, the immunity mechanism of IA algorithm is imported into PSO algorithm to form IA-PSO algorithm. For the purpose of raising fault rate and shortening test pattern generation time, CA algorithm is imported into IA-PSO algorithm to form CAIA-PSO algorithm. Finally, adopting single stuck-at fault and using different algorithms to the simulation experiment of test pattern generation for digital integrated circuits, the result of the experiment is that CA-IA-PSO algorithm can solve the problem of test pattern generation more practically and efficiently, especially the bigger digital integrated circuits.
Sponsorship	Hunan Inst. Ind.
Starting Page	1316
Ending Page	1320
File Size	565224
Page Count	5
File Format	PDF
e-ISBN	9781467371438
DOI	10.1109/ICMTMA.2015.322
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-13
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis IA-PSO algorithm Dictionaries CA algorithm test pattern generation test vector Digital integrated circuits Circuit faults Test pattern generators Integrated circuit modeling Digital circuits
Content Type	Text
Resource Type	Article

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