NDLI: Optimal design of the serial data receiving path

Content Provider	IEEE Xplore Digital Library
Author	Xu Li Miao Ling-Juan Shen Jun
Copyright Year	2011
Description	Author affiliation: School of Automation, Beijing Institute of Technology, 100081, China (Xu Li; Miao Ling-Juan; Shen Jun)
Abstract	Using the Finite State Machines (FSMs) as the core control unit, a serial data receiving scheme based on FPGA is proposed in this paper. The scheme adopts FPGA instead of dedicated chips in digital system to implement asynchronous serial data receiving, and then, to identify and check the data packet in accordance with a certain format. The FSMs described following the coding guidelines of Hardware Description Language (HDL) are introduced to control each module. The design simplifies the circuits, reduces volume, increases data reliability, and more over, processes the data packet by hardware which lightens the processor's calculation load, thus improving digital system's performance. Simulation and practical testing are carried out at last. The results show that the data receiving is accurate and reliable which validates the validity of the design.
Starting Page	4469
Ending Page	4474
File Size	351417
Page Count	6
File Format	PDF
ISBN	9781457706776
ISSN	21612927
e-ISBN	9789881725592
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Chinese Assoc of Automati
Subject Keyword	FSM FPGA Data Packet Digital signal processing Serial Data Receiving Reliability engineering Electronic mail Integrated circuit reliability Hardware design languages Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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