NDLI: Priority inversion detection in Alvis models

Content Provider	IEEE Xplore Digital Library
Author	Baniewicz, J. Szpyrka, M.
Copyright Year	2011
Description	Author affiliation: Department of Automatics, AGH University of Sci. and Techn., Kraków, Poland (Szpyrka, M.) \|\| Delphi Poland S.A., Electronic Controls / E&S, ul. Podgórki Tynieckie 2, 30-399 Kraków, Poland (Baniewicz, J.)
Abstract	Embedded systems verification can be a very challenging task. Most of such systems is composed of subsystems that run concurrently, communicate one with another, compete for shared resources etc. Concurrent systems reveal errors such as deadlocks, livelocks, process starvation and so on. The paper focuses on detection of a priority inversion in Alvis models. Alvis is a novel modelling language defined especially for the embedded systems design and formal verification. Based on CCS and XCCS process algebras, Alvis combines a flexible graphical modelling of interconnections between agents with a high level programming language used for the description of agents behaviour. A priority inversion is a common pitfall in embedded systems. It is hardly possible to detect the problem using tests only. We discuss how the problem can be detected in Alvis models. The discussion is illustrated with real-life examples.
Starting Page	638
Ending Page	643
File Size	318954
Page Count	6
File Format	PDF
ISBN	9781457703041
e-ISBN	9788393207527
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-16
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz
Subject Keyword	Embedded systems Algebra formal verification embedded systems Logic gates Alarm systems priority inversion Batteries Mathematical model Alvis modelling language Vehicles
Content Type	Text
Resource Type	Article

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