NDLI: An FPGA implementation of the asynchronous programmable neighborhood mechanism for WTM Self-Organizing Map

Content Provider	IEEE Xplore Digital Library
Author	Dlugosz, R. Kolasa, M. Szulc, M.
Copyright Year	2011
Description	Author affiliation: Poznań University of Technology, Department of Computer Engineering, Poland (Szulc, M.) \|\| University of Technology and Life Sciences, Faculty of Telecommunication and Electrical Engineering, ul. Kaliskiego 7, 85-796 Bydgoszcz, Poland (Dlugosz, R.; Kolasa, M.)
Abstract	In this paper we present an FPGA-based implementation of the novel architecture of the Kohonen Winner Takes Most (WTM) Self-Organizing Map (SOM) with an asynchronous, programmable neighborhood mechanism. The proposed network is, in general, the synchronous system working in parallel, with some blocks that operate asynchronously. The asynchronous part includes the neighborhood mechanism that ensures the asynchronous spreading of the adaptation enabling signal amongst the neurons neighboring the winning unit. This mechanism is fully programmable and enables runtime adaptation of the neighborhood radius. The overall SOM consists of a controller, the winning neuron selecting unit and the number of neurons that results from the size of the map. The proposed implementation is fully scalable and mostly independent on the size of the map in terms of achievable maximum data rate with only one exception, i.e. the maximum delay introduced by the asynchronous neighborhood mechanism. The delay is linearly dependent on the size of the map. The proposed system has been realized on the Virtex 5 XC5VLX110T device.
Starting Page	258
Ending Page	263
File Size	540349
Page Count	6
File Format	PDF
ISBN	9781457703041
e-ISBN	9788393207527
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-16
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz
Subject Keyword	SOM Kohonen neural networks Neurons Artificial neural networks FPGA implementation Routing Hardware Topology synchronous and asynchronous circuits Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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