NDLI: Analysis of operation of ring LFSR used for testing of unidirectional interleaved interconnections

Content Provider	IEEE Xplore Digital Library
Author	Gucwa, K. Garbolino, T. Hlawiczka, A.
Copyright Year	2011
Description	Author affiliation: Institute of Electronics, Silesian University of Technology, Gliwice, Poland (Gucwa, K.; Garbolino, T.; Hlawiczka, A.)
Abstract	The paper presents analysis of operation of a specific ring LFSR register that can be used to test a network of n interleaved interconnections between modules of digital circuits. This register is a distinctive option of the already known BIST structure referred to as CSTP. When the test is carried out for unidirectional interconnections, the CSTP becomes a linear register and the lines under test make up feedback lines of that register. Due to the fact that layout of these lines looks like the ‘X’ letter that register is referred to as the XR-LFSR. The fault-free XR-LFSR can be reflected by an automaton with the G0 cyclic state diagram and each physical defect f transforms that G0 state diagram into another state diagram Gf ≠ G0. To verify its efficiency for detection of faults the method of state diagram identification was applied. The same authors in previous studies dedicated to bus-type connections observed that the sequence of m states of G0 state diagram, where m > 2n and n > 16, is sufficient to detect a substantial number of static and delay faults for such buses. The present paper comprises the observation that any randomly selected state of the state diagram for the XR-LFSR belongs, with a pretty high level of probability, exceeding 70%, to the cycle with the maximum length cmax. It was also spotted that for n>16 more than 98,4% of all structures lead to sufficiently long cycles cmax > 1000. The both observations confirmed usefulness of XR-LFSRs for testing of unidirectional connections.
Starting Page	479
Ending Page	484
File Size	191443
Page Count	6
File Format	PDF
ISBN	9781457703041
e-ISBN	9788393207527
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-16
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz
Subject Keyword	IBIST XR-LFSR Integrated circuit interconnections BIST Built-in self-test interconnect test ring LFSR (R-LFSR) Polynomials Registers Circuit faults Flip-flops interconnect BIST
Content Type	Text
Resource Type	Article

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