NDLI: Modelling of capacitor mismatch and non-linearity effects ini charge redistribution SAR ADCs

Content Provider	IEEE Xplore Digital Library
Author	Haenzsche, S. Henker, S. Schuffny, R.
Copyright Year	2010
Description	Author affiliation: Neural Circuits and Parallel VLSI-Systems, Technische Univerität Dresden, Germany (Haenzsche, S.; Henker, S.; Schuffny, R.)
Abstract	For embedded high resolution successive approximation ADCs, it is necessary to determine the performance limitation of the CMOS process used for the design. This paper presents a modelling technique for major limitations, i.e. capacitor mismatch and non-linearity effects. The model is besed on Monte Carlo simulations applied to an analytical description of the ADC. Additional effects like charge injection and parasitic capacitance are included. The analytical basis covers different architectures with a fully binary weighted or series-split capacitor array. when comparing our analysis and measurement results to several conventional approaches, a significantly more realistic estimation of the attainable resolution is achieved. The presented results provide guidance in choosing process and circuit structure for the design of SAR ADCs. The model also enbles reliable capacitor sizing early in the design process, i.e. well before actual layout implementation.
Starting Page	300
Ending Page	305
File Size	342276
Page Count	6
File Format	PDF
ISBN	9781424470112
e-ISBN	9788392875642
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-24
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	DEPT OF MICROELECTRON
Subject Keyword	Integrated circuits capacitor matching modeling and simulation Successive approximation register Analog-to-digital-converter ADC CMOS process charge redistribution CR
Content Type	Text
Resource Type	Article

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