NDLI: Device-conscious circuit designs for low-voltage nanoscale CMOS LSIs

Content Provider	IEEE Xplore Digital Library
Author	Itoh, K.
Copyright Year	2010
Description	Author affiliation: Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185-8601, Japan (Itoh, K.)
Abstract	The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vt0, of MOSFETs. As a result of comparing the Vmins of logic, SRAM, and DRAM blocks, it turns out that the SRAM block is problematic because it has the highest Vmin despite using RAM repair techniques. Various techniques are thus reviewed, including shortening the data line, up-sizing the MOSFETs, and control of the common source line or the word line. To further reduce the Vmins of the blocks, ΔVt-immune MOSFETs such as a planar fully-depleted structure (FD-SOI) and fin-type structure (FinFET), and low-Vt0 circuits are discussed, showing the below 0.5-V CMOS era feasible to come.
Starting Page	21
Ending Page	26
File Size	1059985
Page Count	6
File Format	PDF
ISBN	9781424470112
e-ISBN	9788392875642
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-24
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	DEPT OF MICROELECTRON
Subject Keyword	Random access memory FinFET Logic gates Maintenance engineering FD-SOI Nanoscale devices DRAM Timing CMOS integrated circuits The minimum operating voltage SRAM MOSFETs
Content Type	Text
Resource Type	Article

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