NDLI: A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology

Content Provider	IEEE Xplore Digital Library
Author	Dudek, P. Lopich, A. Gruev, V.
Copyright Year	2009
Description	Author affiliation: School of Electrical and Electronic Engineering The University of Manchester United Kingdom (Dudek, P.; Lopich, A.) \|\| Department of Computer Science and Engineering Washington University in St. Louis Missouri, USA (Gruev, V.)
Abstract	This paper presents the design of a vertically-integrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32¥32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits, respectively. The two bottom layers form a mixed-mode cellular processor array, which operates in SIMD mode, and processes the image data acquired by the top-layer backside illuminated photosensor circuit. The intra-processor inter-layer communication is achieved by means of through-silicon vias, and the system is partitioned to minimise the area overhead associated with this communication. The processor comprises 4 analogue and 12 binary registers, and supports arithmetic and logic operations. Various sensor structures have been implemented to evaluate the efficiency of photo-sensing in SOI technology. The prototype circuit measures 2mm¥2mm, with 30μm¥30μm pixel pitch. The architecture and circuit design issues are presented in the paper.
Starting Page	193
Ending Page	196
File Size	734414
Page Count	4
File Format	PDF
ISBN	9781424438969
DOI	10.1109/ECCTD.2009.5274946
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-23
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon on insulator technology Image sensors Logic circuits Prototypes CMOS image sensors CMOS technology CMOS process Registers Through-silicon vias Arithmetic
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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