NDLI: High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems

Content Provider	IEEE Xplore Digital Library
Author	Chang-Seok Choi Hanho Lee
Copyright Year	2009
Description	Author affiliation: Department of Information and Communication Engineering Inha University, Incheon, 402-751, Korea. (Chang-Seok Choi; Hanho Lee)
Abstract	This paper presents a high-speed low-complexity three-parallel Reed-Solomon (RS) decoder for 6-Gbps mmWave WPAN systems. Three-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. Three-way parallelizing for syndrome computation and error correction allow the inputs to be received at very high data rates and the outputs to be delivered at correspondingly high rates with a minimum delay. The proposed three-parallel RS decoder has been implemented 90nm CMOS technology optimized for a 1.2V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400MHz and has a data throughput 9.6-Gbps. The proposed three-parallel RS decoder architecture has a much higher data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6Gbps and beyond.
Starting Page	515
Ending Page	518
File Size	890423
Page Count	4
File Format	PDF
ISBN	9781424438969
DOI	10.1109/ECCTD.2009.5275026
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-23
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reed-Solomon codes Concurrent computing Voltage Throughput CMOS technology Hardware Decoding Error correction Delay Clocks
Content Type	Text
Resource Type	Article

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