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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Delican, Y. Morgul, A. |
| Copyright Year | 2009 |
| Description | Author affiliation: Beykent University, Electrical & Communications Engineering Dept. Istanbul, Turkey (Morgul, A.) || Bogazici University Electrical Engineering Dept. Istanbul, Turkey (Delican, Y.) |
| Abstract | This paper presents a high performance 16x16 bit 2's complement multiplier using MOS Current Mode Logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 μm CMOS technology and VDD of 1.8V. According to our simulations, the highest current circuit works at 800 MHz and consumes 55 mW, while the lowest power operates at 250 MHz and consumes 16 mW. The circuits are either consume less power or operate up to a higher frequency compared to equivalent circuits in the literature. One of the most important advantages of this circuit is the absence of the power supply current spikes which makes the circuit very suitable for mixed mode designs. The multiplier consists of 7,268 transistors while a comparable CMOS multiplier in the literature consists of 13,444 transistors. |
| Starting Page | 157 |
| Ending Page | 160 |
| File Size | 528748 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424438969 |
| DOI | 10.1109/ECCTD.2009.5274960 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-08-23 |
| Publisher Place | Turkey |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS logic circuits Circuit simulation Logic gates Current supplies CMOS technology Libraries Logic design Circuit testing Adders Design optimization |
| Content Type | Text |
| Resource Type | Article |
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