NDLI: A new linear readout circuit for a CMOS image sensor

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2015 European Conference on Circuit Theory and Design (ECCTD)

2013 European Conference on Circuit Theory and Design (ECCTD)

2011 20th European Conference on Circuit Theory and Design (ECCTD)

2009 European Conference on Circuit Theory and Design

Table of contents

APS design alternatives in 0.18μm CMOS image sensor technology

A ring-oscillator-based active quenching and active recharge circuit for single photon avalanche diodes

Double modified internal gate (MIG) pixel for fluorescence imaging applications

A low power CMOS capacitance to pulse duration converter based on a dual clock approach

Behavior of various geometry MagFET structures

Novel electronically tunable FDNR simulator employing single FDCCII

Syllabic companding baseband switched capacitor filter for WLAN 802.11a/g receivers

A novel complex Gm-C IF sub-sampling mixer

A new $2^{nd}$ order variable-state filter: The frequency agile filter

Capacitance spread reduction technique for low-cost switched-capacitor filters implementation

Ultra low power flash ADC for UWB transceiver applications

Adaptive equalization for calibration of subband hybrid filter banks A/D converters

A 14-bit MOS DAC with current sources free from power-line voltage drop and with output circuits free from code-dependent variable time constant

Completely first order and tone free partitioned data weighted averaging technique used in a multibit delta sigma modulator

Dual-edge triggered energy recovery DCCER flip-flop for low energy applications

Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS

Ultra low voltage and high speed CMOS carry generate circuits

Topology selection of FPGA look-up tables for low-leakage operation

Quasi global-equivalence in one-dimensional binary cellular automata

New wave profiles in viscoelastic burgers' RTD-based cellular neural networks model

Variational computing based images denoising methods by using cellular neural networks

Design of new CMOS current mode min and max circuits for FLC chip applications

Locally adaptive image sensing with the 64x64 cell MIPA4k mixed-mode image processor array

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation

A survey on digital background calibration of ADCs

On-chip stimuli generation for ADC dynamic test by ΣΔ technique

New applications and technology scaling driving next generation A/D converters

Signal generators for cost effective BIST of ADCs

Generalized multiplying D/A converter stages for low-power pipelined A/D converters

Design of high-frequency Gm-C wavelet filters

A new OTA-C universal biquad resonates out the main parasitic capacitance

Novel structures of RC-active filters for tapped capacitor resonant circuits

Current-mode SITO filter using a single active component

On the cascade control system tuning for shunt active filters based on modulus optimum criterion

Performance evaluation of LFSR-based spreading sequences with negative auto-correlation designed by Chaos theory of modulo-2 added sequences

Circuit implementation of piecewise-affine functions based on a binary search tree

A parameter-varying lowpass filter with reduced transient response

Dynamic translinear nonlinear energy operator

High performance 16-bit MCML multiplier

High speed VLSI implementation of a finite field multiplier using redundant representation

Hardware efficient fixed-point VLSI architecture for 2D Kurtotic FastICA

A voltage equalizer applying a charge pump for energy storage systems

A focal plane processor for continuous-time 1-D optical correlation applications

Omnidirectional algorithm for the full penetration hole extraction in laser welding processes

The memristive grid outperforms the resistive grid for edge preserving smoothing

3D multi-layer vision architecture for surveillance and reconnaissance applications

Space-dependent binary image processing within a 64x64 mixed-mode array processor

A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology

On a filter bank correction scheme for mitigating mismatch distortions in time-interleaved converter systems

An area-speed efficient method for current mode analog to digital converters

A CMOS 3.2 GB/s serial link transceiver, using PWM and PAM scheme

Design and implementation of operational amplifiers with programmable characteristics in a 90nm CMOS process

A new linear readout circuit for a CMOS image sensor

An eigenvalue study of a double integrator oscillator

A current-mode euclidean distance calculator based on electronically simulated translinear principle

Single-input multi-output resistorless current-mode biquad

A new current-mode square-root-domain notch filter

A CMOS front end for a laser rangefinder with resonance-based timing discrimination

Piecewise-polynomial modeling for analog circuit performance metrics

Modelling the single-electron transistor with piecewise linear functions

Lagrangian modeling of DC-DC buck-boost and flyback converters

SPICE modeling of memristive, memcapacitative and meminductive systems

Properties of silicon carbide schottky diodes under self-heating influence

A low voltage CMOS analog multiplier with high linearity

Compact low-voltage rail-to-rail bulk-driven CMOS opamp for scaled technologies

Input common-mode voltage behaviour of CMOS bulk-driven differential stages

A concurrent quadrature sub-sampling mixer for multiband receivers

Agile frequency synthesizer for cognitive radios

A tunable multi-band CMOS LNA for mobile WiMAX

Spectrum estimator and cyclostattionary detector for cognitive radio

Critical issues and current views on teaching basic circuits and systems in electrical engineering education

Model reduction of linear networks with nonlinear elements

Cascaded lossless commensurate line synthesis

A modified method for circuit analysis using haar wavelet transform with adaptive resolution — For circuits with waveform with sharp convex ranges—

On synthesis of immitance matrices of transformerless RLC networks

Single-ended input four-quadrant multiplier for analog neural networks

Hardware-aware model of sigma-delta cellular neural network

Crosswalks recognition through CNNs for the bionic camera: Manual vs. automatic design

A micropower neural recording amplifier with improved noise efficiency factor

An efficient inverse ANN modeling approach using prior knowledge input with difference method

Improved harmonic balance technique for analysis of ring oscillators

Excitation of multiple spatial modes of a MEMS cantilever in the pulsed digital oscillator

Phase model reduction and synchronization of nonlinear oscillators by a periodic force

Nonlinear analysis of quadrature LC–VCOs

Nonlinear dynamics of alias-locked loop

A new fully differential adaptive CMOS line driver suitable for ADSL applications

Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption

A new technique to achieve exact and controllable voltage gain relations in feedback amplifiers

Differential power analysis attack considering decoupling capacitance effect

Measurement-based equivalent circuit model for ferrite beads

A DRO-based X-band injection-locked amplifier without input non-reciprocal elements

General measurement-based circuit model for symmetrical four-port RF transformers

Analysis of a novel BAW-based power amplifier

GNSScope and the split chip compression technique

A novel topology for the implementation of active distributed multiplexers

A new fault attack on the advanced encryption standard hardware

Empirical comparison of side channel analysis distinguishers on DES in hardware

Differential power analysis of AES ASIC implementations with various S-box circuits

Complementary logics vs masked logics: Which countermeasure is a better selection?

Development of side-channel attack standard evaluation environment

Contact-based fault injections and power analysis on RFID tags

ECG signal compression using wavelet foveation and SPIHT

A nano-power class-AB current multiplier for energy-based action potential detector

Wideband object identification with rectangular wave chirp excitation

Design constraints for the inductive power and data link of an implanted body sensor

Analysis of local activity in reaction-diffusion networks: EEG signals in epilepsy

Steady–state visually evoked EEG signal processing with tuneable continuous–time bandpass sigma–delta modulators

A low-voltage class-AB linear transconductance based on floating-gate MOS technology

Clocked semi-floating-gate pseudo differential pair for low-voltage analog design

Clocked semi-floating-gate ultra low-voltage current multiplier

Analog-digital coincidence mixer for frequency synthesizers

A systematic approach for testing a DAC mismatch shaping method

Pulse width modulation of multilevel delta-sigma output for class S power amplifier

High-performance coherent digital sweep oscillator using piecewise parabolic interpolation

A cooperation index based on correlation matrix spectrum and ráenyi entropy

An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies

Improving convergence of algorithms for solving systems of circuit algebraic-differential equations

Krylov-subspace based model order reduction for field-circuit coupled systems

A direct search method for finding the worst performance measure in integrated circuit design

Improved algorithm for computing all the DC operating points of diode-transistor circuits

Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation

A systematic design procedure for CMOS three-stage NMC amplifiers

Resistive networks for signal and image filtering in the haar basis

Optimizing power-area for constant input-referred noise level in MOSFETs

Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique

High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems

Vertical and horizontal magnetic force sensor and application of sensor in power devices

Low power high performance keeper technique for high fan-in dynamic gates

Mixed-mode behavioral model of flexray physical layer transceiver

Partitioning-based second-order model-order reduction method for RC circuits

Particle filter applied to polynomial chaotic maps

A new modified asymmetric bridge drive circuit switched reluctance motor

A method for searching the limit cycles of high order sigma-delta modulators

Programmable non-linearity for STAR cellular neural networks

Comparison between chua-yang and hyperbolic CNNs

Multidimensional search space for catastrophic faults diagnosis in analog electronic circuits

Implementation of partial synchronization of different chaotic systems by field programmable gate array

Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits

Absolute stability of 2nd order discrete-time single variable lur'e systems

Analysis of periodic solutions of discretized single input sliding mode control systems

Early consensus in complex networks under variable graph topology

Two time-scale approach implemented on hybrid equations

On the synthesis of periodic signals by discrete pulse-trains and optimisation techniques

A low frequency oscillator structure

A novel method for analysis and design of third-order charge pump PLL

Noise and dynamic range of CMOS degenerated active inductor resonators

A performance comparison of dickson and fibonacci charge pumps

Low-sensitivity design and implementation of allpass based fractional delay digital filters

Frequency/time block preconditioners for harmonic balance jacobians

A fuzzy selection based constraint handling method for multi-objective optimization of analog cells

Enhanced multivariate steady-state time-domain method

A generic reconfigurable array specification and programming environment (GRASPER)

A new high speed, low power adder; using hybrid analog-digital circuits

Calculation of cycle lengths in MASH 1-2-2 digital delta sigma modulators with a constant input

Mitigation of the sampling and substrate noise induced distortion in regenerative comparators by adaptive interpolation

A high-speed swing reduced driver suitable for current-steering digital-to-analog converters

Design of stepped-impedance low pass filters with impedance matching by the particle swarm optimization and conjugate gradient method

SAT-based ATPG testing of inter- and intra-gate bridging faults

Multiple catastrophic fault diagnosis of linear circuits considering the component tolerances

A global parametric faults diagnosis with the use of artificial neural networks

Specialised aperiodic excitation and wavelet transform improves analogue fault diagnosis

Faults classification in analog electronic circuits with use of the SVM algorithm

Autonomous third-order duffing-holmes type chaotic oscillator

Experimental study of an interrupted electric circuit with spike noise

Propagation mechanism of phase-inversion wave in 2D lattice oscillators and their application to prediction of time-series data

Design and analysis of a low-power highly linear mixer

Analyses of motion and acceleration sensors using printed spiral inductors by a simulator and actual circuit experiments

Accurate design of a MOS-based resistive network for time-controlled diffusion filtering

Filter approximation problem using de algorithms

A novel wideband-high-CMRR low-voltage BJT current output stage

Class-AB rail-to-rail CMOS buffer with bulk-driven super source followers

A new second-order multi-mode multi-funtion filter using a single CDBA

A new power grid optimization algorithm based on manufacturing cost restriction

Accuracy of the criticality probabilty of a path in statistical timing analysis

Multicore thermal management with model predictive control

A study of CMOS radiation tolerant transistors using green functions

Power efficient polyphase comb decimation filters for ΣΔ modulators in multi-rate digital receivers

A spur-free MASH digital delta-sigma modulator with higher order shaped dither

Quadrature modulator model with third-order non-linearities

An accurate and efficient method for BER analysis in high-speed communication systems

An S band RF digital linearizer for TWTAs and SSPAs

Multi-bit high-order incremental converters with digital calibration

A new scheme for DC offset compensation and its application to current mode and voltage mode D/A converters

A multi-converter DFT technique for complex SIP: Concepts and validation

Design of a 1-V operational passive sigma-delta modulator

Hierarchical synthesis based on pareto-optimal fronts

Qualification and quantification of the nonlinear distortions in discrete-time sigma-delta ADCs

Towards automated extraction of EMC-aware trajectory-based macromodels for analog circuits

Online AMS frontend reconfiguration for sensor network applications

A free-shape router for analog and RF applications

Enhancing analog IC design optimization kernels with simple fuzzy models

Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits

A parametric macromodelling technique

Electromigration-aware design

An application specific circuits design for a LVCSR system

Crosstalk reduction in printed circuit boards using irregularly-spaced vias in a guard trace over a slotted ground plane

Implementation of a visible watermarking in a secure still digital camera using VLSI design

Regional image correspondence matching method for SIMD processing

On the use of memory for detecting musical notes in polyphonic piano music

Sub-band adaptive filtering for acoustic echo cancellation

On clustering coefficients of graphs with the fixed numbers of vertices and edges

Highly reliable harmony search algorithm

Implementation of a parallel SAD based wavefront sensor architecture on FPGA

Computational fluid flow simulation on body fitted mesh geometry with IBM cell broadband engine architecture

An emulated digital wave computer core implementation

A digital cellular-based system for retinal vessel-tree extraction

An efficient FPGA implementation of a DT-CNN for small image gray-scale pre-processing

CNN model on stream processing platform

Insufficiency in finite difference solution of cylindrical time varying magnetic problems

Self-tuning approach to optimization of excitation angles for switched-reluctance motor drives

Design and analysis of low torque ripple switched reluctance motor using 3-dimensional finite element method

Evaluation of hilbert space techniques and lagrange's method for the analysis of dissipated power in DC circuits

Development of a toolbox for frequency response analysis of fractional order control systems

Converting a set into a minimum-phase sequence

Energy-efficent, high-performance viterbi ACS unit implementation in 90nm CMOS

A low power ultra-wideband CMOS LNA with inter stage technique

A single-eletron bandpass digital wave filter

Ising spin-grass error correction for unreliable nanoelectronic logic circuits

Theoretical analysis and characterization of the tunable matching networks in low noise amplifiers

New design of RF MEMS disk resonators and optimization for spurious modes

A noise shaped flash time to digital converter for all digital frequency synthesizers

Brayton - Moser's equations of transmission line circuits and their complete stability

To the memory of

2007 18th European Conference on Circuit Theory and Design

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.

A new linear readout circuit for a CMOS image sensor

Content Provider	IEEE Xplore Digital Library
Author	Teymouri, M. Hadidi, K. Khoei, A.
Copyright Year	2009
Description	Author affiliation: Microelectronics Research Center Urmia University Urmia - Iran (Teymouri, M.; Hadidi, K.; Khoei, A.)
Abstract	This paper presents a high linearity, low area and low power column-parallel readout circuit with a modified 3 transistor active pixel sensor (3T-APS). Each column readout circuit consumes 43uW power provided from the 3.3V power supply and a small layout size of $10x300um^{2}$ is integrated in the 512 columns at one side of the pixel array. The modified pixel achieves the signal saturation voltage is the same as the standard APS structure, and the readout circuit linearity range is 99.9%. A high linearity 512x512 pixel CMOS image sensor with the proposed column-parallel readout circuit is designed based on 0.35um 2P4M standard CMOS technology.
Starting Page	213
Ending Page	216
File Size	480651
Page Count	4
File Format	PDF
ISBN	9781424438969
DOI	10.1109/ECCTD.2009.5274955
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-23
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image quality Circuits Linearity Switches CMOS image sensors Dynamic range CMOS technology Threshold voltage Equations Pixel
Content Type	Text
Resource Type	Article

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