NDLI: Organic Computing at the System on Chip Level

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2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

2007 IFIP International Conference on Very Large Scale Integration

2006 IFIP International Conference on Very Large Scale Integration

Proceedings contents

Welcome to IFIP VLSI-SOC 2006

Program Committee

The system is really in the SoC : new investment opportunities

An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize them

Design challenges for the 45 nm node and below

Introduction to panel discussion Probabilistic & statistical design - the wave of the future

Table of contents

Probabilistic CMOS Technology: A Survey and Future Directions

Can Asynchronous Techniques Help the SoC Designer?

State-holding in Look-Up Tables: application to asynchronous logic

MDCT IP Core Generator with Architectural Model Simulation

A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures

Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging

Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits

Circuit and Device Technologies for CMOS functional Image Sensors

Oversampled Time Estimation Techniques for Precision Photonic Detectors

Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV

High-Throughput Montgomery Modular Multiplication

A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation

An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures

Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow

Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip

A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes

Signal Coverage Computation in Formal Verification

Modelling Heterogeneous Interactions in SoC Verification

PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking

A Fast SAT Solver Strategy Based on Negated Clauses

On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems

Variation-Aware, Library Compatible Delay Modeling Strategy

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias

A VHDL Generation Tool for Optimized Parallel FIR Filters

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Detecting DNA by field effect transistor arrays

Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices

Human++: Emerging Technology for Body Area Networks

Security evaluation of dual rail logic against DPA attacks

A low power high performance CMOS voltage-mode quaternary full adder

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing

Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor

A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology

Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture

Architecture of an HDTV Intraframe Predictor for a H.264 Decoder

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

BIST Scheme for Low Heat Dissipation and Reduced Test Application Time

The Demand and Practical Approach for 100x Test Compression

Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems

Directed Convergence Heuristic: A fast & novel approach to Steiner Tree Construction

Technical Documentation of Software and Hardware in Embedded Systems

Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator

Pseudo Floating-Gate Inverter with Feedback Control

Main Memory Energy Optimization for Multi-Task Applications

EXOR Projected Sum of Products

Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures

Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits

Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

CAT platform for analogue and mixed-signal test evaluation and optimization

Study of a BIST Technique for CMOS Active Pixel Sensors

Soft Error Resilient System Design through Error Correction

Organic Computing at the System on Chip Level

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design

A New Phase Noise Model for TSPC based divider

A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs

A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFD

Energy-Effcient Scheduling for Autonomous Mobile Robots

Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design

System-level Dynamic Power Management Techniques for Communication Intensive Devices

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation

SOC Debug Challenges and Tools

Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis

On-Line Test Vector Generation from Temporal Constraints Written in PSL

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Organic Computing at the System on Chip Level

Content Provider	IEEE Xplore Digital Library
Author	Bouajila, A. Zeppenfeld, J. Stechele, W. Herkersdorf, A. Bernauer, A. Bringmann, O. Rosenstiel, W.
Copyright Year	2006
Description	Author affiliation: Inst. for Integrated Syst., Munich Univ. of Technol. (Bouajila, A.; Zeppenfeld, J.; Stechele, W.; Herkersdorf, A.)
Abstract	The evolution of CMOS technologies leads to integrated circuits with ever smaller device sizes, lower supply voltage, higher clock frequency and more process variability. Intermittent faults effecting logic and timing are becoming a major challenge for future integrated circuit designs. This paper presents an organic computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques. We demonstrate the feasibility of this approach by example on the processing pipeline of a public-domain RISC CPU core
Starting Page	338
Ending Page	341
File Size	311814
Page Count	4
File Format	PDF
ISBN	3901882197
DOI	10.1109/VLSISOC.2006.313257
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	IFIP
Subject Keyword	Integrated circuit technology CMOS logic circuits Voltage CMOS technology CMOS process Frequency CMOS integrated circuits System-on-a-chip Circuit faults Clocks
Content Type	Text
Resource Type	Article

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