NDLI: A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Content Provider	IEEE Xplore Digital Library
Author	Del Valle, P.G. Atienza, D. Magan, I. Flores, J.G. Perez, E.A. Mendias, J.M. Benini, L. De Micheli, G.
Copyright Year	2006
Description	Author affiliation: DACYA, UCM, Madrid (Del Valle, P.G.)
Abstract	With the growing complexity in consumer embedded products and the improvements in process technology, multiprocessor system-on-chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Therefore, mechanisms to efficiently explore the different possible HW-SW design interactions in complete MPSoC systems are in great need. In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our results show that the proposed framework is able to extract a number of critical statistics from processing cores, memory and interconnection systems, with a speed-up of three orders of magnitude compared to cycle-accurate MPSoC simulators
Starting Page	140
Ending Page	145
File Size	435610
Page Count	6
File Format	PDF
ISBN	3901882197
DOI	10.1109/VLSISOC.2006.313218
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	IFIP
Subject Keyword	Real time systems Energy consumption Costs Emulation Embedded system Time to market System-on-a-chip Statistics Hardware design languages Context modeling
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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