NDLI: Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture

Content Provider	IEEE Xplore Digital Library
Author	Pandey, S. Utlu, N. Glesner, M.
Copyright Year	2006
Description	Author affiliation: Inst. of Microelectron. Syst., Darmstadt Univ. of Technol. (Pandey, S.; Utlu, N.; Glesner, M.)
Abstract	This paper presents a method of on-chip communication bus topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We define the problem of on-chip communication topology synthesis into two main problems namely scheduling and allocation binding problem. The communication behavior of each module is modeled as a set of communication lifetime intervals (CLTIs), which are evaluated and scheduled for different size of bus width to get the minimum number of overlaps, minimum size of bus width and the minimum number of bus(es) using tabu search method. These optimized CLTIs are given to the clique partitioning algorithm as an allocation-binding problem to synthesize the communication topology
Starting Page	222
Ending Page	227
File Size	6238532
Page Count	6
File Format	PDF
ISBN	3901882197
DOI	10.1109/VLSISOC.2006.313237
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	IFIP
Subject Keyword	Software libraries Protocols Search methods Hardware Software standards Topology Partitioning algorithms Microelectronics Decoding System-on-a-chip
Content Type	Text
Resource Type	Article

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