NDLI: Low-speed scan testing of charge-sharing faults for CMOS domino circuits

Content Provider	IEEE Xplore Digital Library
Author	Cheng, C.H. Jone, W.B. Wang, J.S. Chang, S.C.
Copyright Year	2000
Description	Author affiliation: Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan (Cheng, C.H.)
Abstract	Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design high-performance processors. However, domino logic suffers from several design problems and one of the most notable ones is the charge-sharing problem. Charge sharing may degrade output voltage level or even cause erroneous output value (named as charge-sharing fault). In this work, we find that charge-sharing faults are extremely resistant to scan test. In fact, charge-sharing faults occurring at the border gates cannot be detected by any scan method, due to the missing error caused by early signal arrival time. Further, we show that killing error might happen in charge-sharing fault detection for both border gates and non-border gates because of the low-speed testing problem caused again by scan test. We thoroughly investigate both test errors and propose two design-for-testability techniques to efficiently eliminate both problems.
Starting Page	329
Ending Page	337
File Size	573674
Page Count	9
File Format	PDF
ISBN	0769507190
ISSN	10636722
DOI	10.1109/DFTVS.2000.887173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults CMOS logic circuits Capacitance CMOS process Voltage Clocks Computer science Logic design Inverters
Content Type	Text
Resource Type	Article

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