NDLI: Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design

Content Provider	IEEE Xplore Digital Library
Author	Se Hun Kim Mooney, V.J.
Copyright Year	2006
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA (Se Hun Kim; Mooney, V.J.)
Abstract	For the most recent CMOS feature sizes (e.g., 90nm and 65nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption as presented in ITRS by Semiconductor Industry Association, 2005. We propose a novel approach, named "sleepy keeper," which reduces leakage current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus two additional transistors - driven by a gate's already calculated output - to save state during sleep mode. Dual $V_{th}$ values can be applied to sleepy keeper in order to dramatically reduce subthreshold leakage current. In short, like the sleepy stack approach, sleepy keeper achieves leakage power reduction equivalent to the sleep and zigzag approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered). Based on experiments with a 4-bit adder circuit, sleepy keeper approach achieves up to 49% less delay and 49% less area than the sleepy stack approach. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon in a VLSI designer's arsenal
Starting Page	367
Ending Page	372
File Size	382386
Page Count	6
File Format	PDF
ISBN	3901882197
DOI	10.1109/VLSISOC.2006.313263
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	IFIP
Subject Keyword	Energy consumption Circuits Electronics industry Very large scale integration Leakage current Power dissipation Logic Subthreshold current Adders Delay
Content Type	Text
Resource Type	Article

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