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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chih-Yun Pai Li, K.S.-M. |
| Copyright Year | 2010 |
| Abstract | This paper proposes a resilient scheme to achieve maximal interconnect fault tolerance, reliability and yield for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this scheme can tolerate faulty connections by efficiently finding alternative paths with modified Longest Common Subsequence. This scheme is compatible with previous interconnect detection and diagnosis methods, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple faults. Furthermore, this scheme can identify connections which will cause communication failure if they are faulty. With this knowledge, designers can significantly improve interconnect reliability by augmenting such vulnerable connections. Experimental results show that alternative paths can be found for almost all paths in this scheme, this it provides a way to achieve fault-tolerant and reliability/yield improvement. |
| Starting Page | 261 |
| Ending Page | 266 |
| File Size | 419877 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424488414 |
| ISSN | 10817735 |
| DOI | 10.1109/ATS.2010.53 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-01 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Resilience Maintenance engineering Oscillators System-on-a-chip Fault tolerance Fault tolerant systems Integrated circuit interconnections fault-tolerant routing interconnect resilience interconnect diagnosis interconnect detection oscillation ring |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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