NDLI: Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

Content Provider	IEEE Xplore Digital Library
Author	Haghbayan, M.H. Karamati, S. Javaheri, F. Navabi, Z.
Copyright Year	2010
Abstract	In this paper we are revisiting the issue of sequential circuit test generation, and use a selective random pattern test generation method implemented in an HDL environment. The method uses a statistical expectation graph and states of the sequential circuit for selecting the appropriate test vectors to achieve better fault coverage and a more compact test set. To further reduce the size of the generated test set, a static compaction method, which is also implemented in an HDL environment, is used after the test generation process. The experimental results show that selecting good test patterns among random test patterns, not only can be implemented dynamically in an HDL design environment, but also results in a better fault coverage and shorter test pattern length in comparison with some traditional deterministic methods. In addition, it will be shown that static test set compaction methods can considerably reduce the test length of test patterns for sequential designs obtained by our proposed method.
Starting Page	53
Ending Page	56
File Size	365124
Page Count	4
File Format	PDF
ISBN	9781424488414
ISSN	10817735
DOI	10.1109/ATS.2010.85
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Compaction Sequential circuits Hardware design languages Silicon Integrated circuit modeling Testing compaction sequential circuit random test generation PLI shortest sequence expectation graph
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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