NDLI: We Need Faster & Deeper Scan and More Realistic Tests

Content Provider	IEEE Xplore Digital Library
Author	Rivoir, J.
Copyright Year	2008
Description	Author affiliation: Verigy Germany GmbH (Rivoir, J.)
Abstract	A hundredfold increase of scan data volume has been predicted for the next ten years. This position statement discusses the implications on ATE and EDA, within the constraints of test cost, quality, and time-to-market. The first conclusion will be that the demand for more scan data can be met without increasing test cost, by exploiting test data sharing across multiple equal cores, relying on improved test data compression, and on faster scan I/O, served by deeper ATE memory. But will this provide sufficient test coverage? It seems too challenging to create effective, up-to-date fault models and suitable scan test conditions such that practical ATPG alone can successfully target all defects in future complex heterogeneous SiP and 3D packages. Additional new test methodologies will be needed to test devices under stressful realistic conditions. ATE must provide well controllable stress test conditions and interact with the DUT at a higher level of abstraction to enable fast development of system-like tests.
Starting Page	1
Ending Page	2
File Size	690402
Page Count	2
File Format	PDF
ISBN	9781424424023
ISSN	10893539
DOI	10.1109/TEST.2008.4700669
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Electronic design automation and methodology Pins CMOS technology System testing Time to market Test data compression Automatic test pattern generation Packaging Stress control
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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