NDLI: Low Energy On-Line SBST of Embedded Processors

Content Provider	IEEE Xplore Digital Library
Author	Merentitis, A. Kranitis, N. Paschalis, A. Gizopoulos, D.
Copyright Year	2008
Description	Author affiliation: Dept. of Inf. & Telecommun., Univ. of Athens, Athens (Merentitis, A.; Kranitis, N.; Paschalis, A.) \|\| Dept. of Inf., Univ. of Piraeus, Piraeus (Gizopoulos, D.)
Abstract	Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical applications. Among the various systems that fall in the previous category, wireless sensor networks (WSN) are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly increased, thus on-line and in-field testing is necessary to guarantee the accuracy of the sensed values. At the same time, on-line testing of processors integrated in WSN has the extra requirement of minimum energy consumption, because these devices are operating on battery, cannot be connected to any external power supply, and the battery duration determines the lifetime of the system. In this paper we present a methodology for the optimization of SBST routines from the energy perspective. Techniques utilized for achieving energy reduction include energy aware loop synthesis, loop transformations, instruction substitution and register renaming. Simulation results show that the energy savings at processor level are up to 35.6%.
Starting Page	1
Ending Page	10
File Size	429182
Page Count	10
File Format	PDF
ISBN	9781424424023
ISSN	10893539
DOI	10.1109/TEST.2008.4700581
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless sensor networks System testing Batteries Built-in self-test Automatic testing Software testing Application software Hazards Life testing Energy consumption
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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