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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yen-Tzu Lin Poku, O. Blanton, R.D. Nigh, P. Lloyd, P. Iyengar, V. |
| Copyright Year | 2008 |
| Description | Author affiliation: IBM Syst. & Technol. Group, Essex, VT (Nigh, P.; Lloyd, P.; Iyengar, V.) || Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA (Yen-Tzu Lin; Poku, O.; Blanton, R.D.) |
| Abstract | Physically-aware N-detect attempts to improve the detection characteristics of traditional N-detect by exploiting the localized characteristics of defects. Specifically, in addition to detecting each fault N times, we also require that the physical neighborhood surrounding the target change state as well. In this work, the effectiveness of the physically-aware metric is examined using two approaches. First, tester responses from an in-production IBM chip are analyzed to compare the physically-aware N-detect test with other traditional tests that include stuck-at, IDDQ, logic BIST, and delay tests. Second, diagnostic results from LSI chip failures are utilized to directly compare the traditional and physically-aware N-detect metrics. Results from both experiments demonstrate the effectiveness of physically-aware N-detect test in detecting defects in modern industrial designs. |
| Starting Page | 1 |
| Ending Page | 9 |
| File Size | 904673 |
| Page Count | 9 |
| File Format | |
| ISBN | 9781424424023 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.2008.4700606 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-10-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Fault detection Logic testing Large scale integration Costs Delay Clocks System testing Built-in self-test Application specific integrated circuits |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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