NDLI: Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors

Content Provider	IEEE Xplore Digital Library
Author	Sinanoglu, O.
Copyright Year	2008
Description	Author affiliation: Math. & Comput. Sci. Dept., Kuwait Univ. (Sinanoglu, O.)
Abstract	While test stimulus compression helps reduce test time and data volume, and thus alleviates test costs, the delivery of certain test vectors may not be possible, leading to test quality degradation. Whether a test vector is encodable in the presence of a decompressor strongly hinges on the distribution of its care bits. In this paper, we present a technique that provides an on-chip capability to judiciously manipulate care bit distribution of a test vector. We thus propose a hardware block, namely, Align-Encode, to be utilized along with any decompressor to boost the effectiveness of the decompressor. Align-Encode is reconfigured on a per pattern basis to delay the shift-in operations in selected scan chains, in order to align the scan slices in such a way that more test vectors become encodable. The reconfigurability of Align-Encode provides a test pattern independent solution, wherein any given set of test vectors can be analyzed to compute the proper delay information. We map the delay computation problem to the maximal clique problem, and utilize an efficient heuristic to provide a near-optimal solution. Experimental results also justify the test pattern encodability enhancements that Align-Encode delivers, enabling significant test quality improvements and/or test cost reductions even when used with simple decompressors.
Starting Page	1
Ending Page	10
File Size	1358413
Page Count	10
File Format	PDF
ISBN	9781424424023
ISSN	10893539
DOI	10.1109/TEST.2008.4700647
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Testing Costs Delay Degradation Hardware Pins Mathematics Computer science Fasteners
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Scan Architecture With Align-Encode

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments

Improving test compression by retaining non-pivot free variables in sequential linear decompressors

Optimal Seguencing of Scan Registers

Pattern Encodability Enhancements for Test Stimulus Decompressors

Test path simulation and characterisation

R4X/D4X-formatters for flexible test system architecture

Impact Of Boundary-Scan Design On Delay Test

X-Align: Improving the Scan Cell Observability of Response Compactors

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors

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Scan Architecture With Align-Encode

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments

Improving test compression by retaining non-pivot free variables in sequential linear decompressors

Optimal Seguencing of Scan Registers

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Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors