NDLI: Testing Techniques for Hardware Security

Content Provider	IEEE Xplore Digital Library
Author	Majzoobi, M. Koushanfar, F. Potkonjak, M.
Copyright Year	2008
Description	Author affiliation: Comput. Sci. Dept., Univ. of California Los Angeles, Los Angeles, CA (Potkonjak, M.) \|\| Electr. & Comput. Eng. Dept., Rice Univ., Houston, TX (Majzoobi, M.; Koushanfar, F.)
Abstract	System security has emerged as a premier design requirement. While there has been an enormous body of impressive work on testing integrated circuits (ICs) desiderata such as manufacturing correctness, delay, and power, there is no reported effort to systematically test IC security in hardware. Our goal is to provide an impetus for this line of research and development by introducing techniques and methodology for rigorous testing of physically unclonable functions (PUFs). Recently, PUFs received a great deal of attention as security mechanisms due to their flexibility to form numerous security protocols and intrinsic resiliency against physical and side channels attacks. We study three classes of PUFs properties to design pertinent test methods: (i) predictability, (ii) sensitivity to component accuracy, and (iii) susceptibility to reverse engineering. As our case studies, we analyze two popular PUF structures, linear and feed-forward, and show that their security is not adequate from several points of view. The technical highlights of the paper are the first non-destructive technique for PUF reverse engineering and a new PUF structure that is capable of passing our security tests.
Starting Page	1
Ending Page	10
File Size	296282
Page Count	10
File Format	PDF
ISBN	9781424424023
ISSN	10893539
DOI	10.1109/TEST.2008.4700636
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Circuit testing Power system security Integrated circuit testing System testing Reverse engineering Integrated circuit manufacture Delay Research and development Protocols
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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