NDLI: Linearity Test of Analog-to-Digital Converters Using Kalman Filtering

Content Provider	IEEE Xplore Digital Library
Author	Le Jin Degang Chen Randall Geiger
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA (Le Jin; Degang Chen; Randall Geiger)
Abstract	This work introduces an efficient code-density linearity testing algorithm for ADCs that can achieve high accuracy within short test time. The proposed algorithm uses Kalman filtering to suppress the effect of errors in the histogram counts based on characteristics of input noise and circuit mismatches. Appropriate versions of the algorithm for ADCs of flash and pipelined architectures are introduced respectively. Simulation results show that this approach can reduce the $INL_{k}$ estimation error by over 50% and achieve desired accuracy with a much smaller number of samples as compared to the conventional algorithm. Simulation and experimental results show that the proposed algorithm can significantly shorten the linearity test time by a factor of 10 or higher. Therefore, it can enable test and help maintain the quality of high-performance ADCs, and reduce the production test time and cost for medium and low resolution ADCs
Starting Page	1
Ending Page	9
File Size	805136
Page Count	9
File Format	PDF
ISBN	1424402913
ISSN	10893539
DOI	10.1109/TEST.2006.297679
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linearity Analog-digital conversion Kalman filters Circuit testing Filtering algorithms Histograms Circuit noise Circuit simulation Estimation error Production
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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