NDLI: Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing

Content Provider	IEEE Xplore Digital Library
Author	Liau Chee Hong, E. Menke, M. Janik, T. Schmitt-Landsiedel, D.
Copyright Year	2006
Description	Author affiliation: Infineon Technol. AG, Neubiberg (Liau Chee Hong, E.; Menke, M.; Janik, T.)
Abstract	This paper describes a novel computational intelligence test method with automatic pattern size reduction algorithm - Pattern Pruner for improving the efficiency of localization for the design weaknesses and/or faults using state-of-art automatic test equipment (ATE). Computational intelligence and Pattern Pruner software implemented on semiconductor automatic test equipment allows finding worst case test pattern and identifying design weaknesses. This is demonstrated by detection of a hang-up in a pseudo-SRAM test chip with asynchronous operation and hidden refresh, package parasitics are found to be the cause of the failure, and debugging is performed by modification of the power network
Starting Page	1
Ending Page	10
File Size	519649
Page Count	10
File Format	PDF
ISBN	1424402913
ISSN	10893539
DOI	10.1109/TEST.2006.297653
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational intelligence Competitive intelligence Automatic testing Automatic test equipment Algorithm design and analysis Semiconductor device testing Software testing Semiconductor device packaging Packaging machines Debugging
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A novel semiconductor test equipment concept: automatic test equipment with computational intelligence technique (ATE-CIT)

DFFT design for functional testability

A procedural interface to test

Computational intelligence based testing for semiconductor measurement systems

A pattern skipping method for weighted random pattern testing

Solving static related problems in packaging, marking, and test

CFD analysis of automatic test equipment

Semiconductor perspective on test standards

How we test Siemens Embedded DRAM Cores

Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing

Similar Documents

A novel semiconductor test equipment concept: automatic test equipment with computational intelligence technique (ATE-CIT)

DFFT design for functional testability

A procedural interface to test

Computational intelligence based testing for semiconductor measurement systems

A pattern skipping method for weighted random pattern testing

Solving static related problems in packaging, marking, and test

CFD analysis of automatic test equipment

Semiconductor perspective on test standards

How we test Siemens Embedded DRAM Cores

Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing