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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Syal, M. Chandrasekar, K. Vimjam, V. Hsiao, M.S. Yi-Shing Chang Chakravarty, S. |
| Copyright Year | 2006 |
| Abstract | This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. Its impact on reducing the overkill in testing was analyzed, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, it was shown that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, the evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes |
| Starting Page | 1 |
| Ending Page | 10 |
| File Size | 324770 |
| Page Count | 10 |
| File Format | |
| ISBN | 1424402913 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.2006.297667 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-10-22 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Circuit faults Automatic test pattern generation Algorithm design and analysis Design for testability Power generation Fault diagnosis State-space methods Binary decision diagrams Computational modeling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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