NDLI: Advanced embedded memory testing: Reducing the defect per million level at lower test cost

Content Provider	IEEE Xplore Digital Library
Author	Hamdioui, S. van de Goor, A.J.
Copyright Year	2010
Description	Author affiliation: Delft University of Technology, Computer Engineering Laboratory, Mekelweg 4, 2628 CD, Delft, The Netherlands (Hamdioui, S.; van de Goor, A.J.)
Abstract	Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of deviceparameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality. The objective of this embedded tutorial is to provide test engineers, memory and ASIC designers, researchers, students and managers with an overview of state-of-the art of fault models for SRAMs (including traditional fault modeling and recent development in fault models for current and future technologies), together with the latest test algorithms. Next, it describes test plans, which are shown to depend on the size of the SRAM, its speed, and the application domain. Thereafter, industrial results are used to show the effectiveness of the proposed algorithms and stresses. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.
Starting Page	7
Ending Page	7
File Size	297875
Page Count	1
File Format	PDF
ISBN	9781424466122
e-ISBN	9781424466139
DOI	10.1109/DDECS.2010.5491828
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Costs System-on-a-chip Semiconductor device manufacture Nanotechnology Failure analysis Design engineering Memory management Application specific integrated circuits Algorithm design and analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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