NDLI: Test scheduling for modular SOCs in an abort-on-fail environment

Content Provider	IEEE Xplore Digital Library
Author	Ingelsson, U. Goel, S.K. Larsson, E. Marinissen, E.J.
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci., Linkopings Univ., Linkoping, Sweden (Ingelsson, U.)
Abstract	Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module's manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC'02 SOC test benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction of the expected test application time, without any modification of the SOC or ATE.
Starting Page	8
Ending Page	13
File Size	203015
Page Count	6
File Format	PDF
ISBN	0769523412
DOI	10.1109/ETS.2005.38
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-22
Publisher Place	Estonia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit testing Circuit testing Job shop scheduling System testing Costs Pulp manufacturing Semiconductor device testing Benchmark testing Semiconductor device manufacture Application specific integrated circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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