NDLI: Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Straka, M. Kastil, J. Kotasek, Z.
Copyright Year	2010
Description	Author affiliation: Faculty of Information Technology, Brno University of Technology, Bozetechova 2, Brno, 612 66, Czech Republic (Straka, M.; Kastil, J.; Kotasek, Z.)
Abstract	Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.
Starting Page	173
Ending Page	176
File Size	300485
Page Count	4
File Format	PDF
ISBN	9781424466122
e-ISBN	9781424466139
DOI	10.1109/DDECS.2010.5491793
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Field programmable gate arrays Fault tolerant systems Circuit faults Redundancy Fault detection Electrical fault detection Hardware Vehicle dynamics Reconfigurable logic partial reconfiguration fault tolerant on-line checker architecture triple modular redundancy duplex FPGA
Content Type	Text
Resource Type	Article

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