NDLI: Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing

Content Provider	IEEE Xplore Digital Library
Author	Kastil, J. Korenek, J.
Copyright Year	2010
Description	Author affiliation: Faculty of Information Technology, Brno University of Technology, Bozetechova 2, Brno, 612 66, Czech Republic (Kastil, J.; Korenek, J.)
Abstract	With the increased amount of data transferred by computer networks, the amount of the malicious traffic also increases and therefore it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. Pattern matching is the time critical operation of current IDS. This paper deals with the analysis of regular expressions used by modern IDS to describe malicious traffic. According to our analysis, more than 64 percent of regular expressions create Deterministic Finite Automaton (DFA) with less than 20 percent of saturation of the transition table which allows efficient implementation of pattern matching into FPGA platform. We propose architecture for fast pattern matching using perfect hashing suitable for implementation into FPGA platform. The memory requirements of presented architecture is closed to the theoretical minimum for sparse transition tables.
Starting Page	149
Ending Page	152
File Size	294510
Page Count	4
File Format	PDF
ISBN	9781424466122
e-ISBN	9781424466139
DOI	10.1109/DDECS.2010.5491796
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Acceleration Pattern matching Automata Intrusion detection Telecommunication traffic Field programmable gate arrays Computer networks Protection Computer security Deterministic Finite Automata Inrusion Detection Perfect hashing hardware acceleration
Content Type	Text
Resource Type	Article

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