NDLI: A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Content Provider	IEEE Xplore Digital Library
Author	Kuo-Hsing Cheng Chang-Chien Hu Jen-Chieh Liu Hong-Yi Huang
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering, National Central University, Taiwan (Kuo-Hsing Cheng; Chang-Chien Hu; Jen-Chieh Liu) \|\| Graduate Institute of Electrical Engineering, National Taipei University, Taiwan (Hong-Yi Huang)
Abstract	This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.
Starting Page	285
Ending Page	288
File Size	670188
Page Count	4
File Format	PDF
ISBN	9781424466122
e-ISBN	9781424466139
DOI	10.1109/DDECS.2010.5491766
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Timing Pulse amplifiers Space vector pulse width modulation Clocks Phase frequency detector Digital control Digital-controlled oscillators Delay lines Signal resolution all digital PLL (ADPLL) time-to-digital (TDC) multi-phase digital controlled oscillator (DCO)
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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