NDLI: Reduction of power dissipation through parallel optimization of test vector and scan register sequences

Content Provider	IEEE Xplore Digital Library
Author	Kotasek, Z. Skarvada, J. Strnadel, J.
Copyright Year	2010
Description	Author affiliation: Brno University of Technology, Faculty of Information Technology, Božet¿chova 2, 61266 Brno, Czech Republic (Kotasek, Z.; Skarvada, J.; Strnadel, J.)
Abstract	In the paper, novel method for reducing power dissipation during test application time is presented. When compared to existing methods, its advantage can be seen in the fact that power dissipation is evaluated by means of precise and fast simulation based metric rather than by means of commonly utilized simple metric based on evaluating Hamming distance between test vectors. In our method, the metric is evaluated over CMOS primitives from AMI technological libraries. In order to reduce power dissipation, the sequence of test vectors to be applied and proper ordering of registers within scan chains are optimized. In existing approaches, the optimizations are typically performed separately in a sequence because problems they correspond to are seen to be independent. On contrary to that, we have united the search spaces and solved these two problems as a single optimization task. Genetic algorithm operating over an appropriate encoding of the problem was utilized to optimize the problem. Proposed method was implemented in both single and multiprocessor environments and it was successfully tested to cooperate with commercial tools. At the end of the paper, results achieved over benchmarks from ISCAS85, ISCAS89 and ITC99 sets are presented and compared to results of existing methods.
Starting Page	364
Ending Page	369
File Size	334052
Page Count	6
File Format	PDF
ISBN	9781424466122
e-ISBN	9781424466139
DOI	10.1109/DDECS.2010.5491750
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Circuit testing Optimization methods Genetic algorithms Power supplies Threshold voltage Paper technology Information technology Hamming distance Ambient intelligence search space investigation power dissipation test set reorganization scan chain reordering test application time genetic algorithm optimization
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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