NDLI: A novel soft error mitigation approach for SRAM-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Lutzel, Sascha Siemers, Christian
Copyright Year	2012
Description	Author affiliation: Department of Informatics, Clausthal University of Technology, Julius-Albert-Straße 4, 38678 Clausthal-Zellerfeld, Germany (Lutzel, Sascha; Siemers, Christian)
Abstract	SRAM-based FPGA devices are susceptible to Single Event Effects (SEE) inside configuration memory. Most approaches for soft error mitigation use Triple Modular Redundancy (TMR) to avoid the consequences of these errors. The drawback is that TMR implementation results in a triplication of required hardware and therefore TMR increases the power consumption. This paper describes a novel approach of soft error mitigation technique for SRAM-based Field Programmable Gate Arrays without using the Triple Modular Redundancy approach. Based on additional logic storing the correct states, it is capable of detecting Single Event Upsets (SEUs), reconfiguring the system and to correct the detected errors via rollback to the last known correct state. The approach was implemented as a prototype and this paper describes the first results of our research and shows that it is possible to mitigate soft errors in a efficient way but not with the same safety level TMR does.
Starting Page	1
Ending Page	6
File Size	408400
Page Count	6
File Format	PDF
ISBN	9781467344975
ISSN	21544824
e-ISBN	9781889334479
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-24
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	TSI Press
Subject Keyword	Field programmable gate arrays Error analysis Tunneling magnetoresistance Error correction codes Timing Hardware Memory management
Content Type	Text
Resource Type	Article

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