NDLI: Two-Dimensional Dynamic Multigrained Reconfigurable Hardware

Content Provider	IEEE Xplore Digital Library
Author	Braun, L. Becker, J.
Copyright Year	2010
Abstract	Partial dynamic reconfigurable (PDR) systems designed with state-of-the-art tool chains, like the Early Access Partial Reconfiguration (EAPR) Flow from Xilinx \cite{UG208}, don't exploit the flexibility provided by dynamic an partial reconfiguration features a state of the art FPGA chip offers. For example the utilized chip area and the position for a dynamic area on the chip is traditionally fixed during design-time. Thereby the shape and the size of the area is given by the largest module. If a smaller module is placed on the region of a bigger one, chip area stays unused. These mentioned restrictions are only some examples for the current support of development and run-time tools for reconfigurable hardware architectures. A new approach is shown for exploiting the capability of reconfigurable hardware architectures more efficient than other solutions introduced before. This is achieved through a novel concept of using micro blocks for the communication infrastructure as well as for the functional elements on the FPGA. The granularity of the micro blocks for building up more complex structures on the FPGA is discussed in this paper.
Starting Page	475
Ending Page	476
File Size	135700
Page Count	2
File Format	PDF
ISBN	9781424473212
e-ISBN	9781424473205
DOI	10.1109/ISVLSI.2010.9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Field programmable gate arrays Routing Memory management System-on-a-chip Resource management
Content Type	Text
Resource Type	Article

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