NDLI: An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division

Content Provider	IEEE Xplore Digital Library
Author	Petrellis, N. Birbas, M. Kikidis, J. Birbas, A.
Copyright Year	2010
Abstract	An 8-bit subrange Analog to Digital Converter (ADC) designed in a CMOS TSMC90nm process consisting of a coarse 4-bit and a fine 4-bit ADC stage is presented in this paper. It occupies only 0.04mm2 of die area and dissipates less than 22mW without sacrificing speed since the sampling rate is higher than 500MS/s and the achieved SNDR is higher than 40dB. These features have been estimated by post-layout simulations. In ordinary subrange architectures a Digital to Analog Converter (DAC) generates an analog value from the digital coarse ADC output that is subtracted by the input in order to produce a residue that serves as input to the fine ADC stage. In such an approach, the linearity errors of the coarse ADC, the DAC and the subtractor are accumulated. In the present work, a voltage mode modulo-16 integer divider is used at the input of the subrange ADC and a “thermometer to binary encoder” that is driven directly by the comparator outputs of the integer divider is also employed instead of a full 4-bit coarse ADC, leading to an ultra low area and power design with less linearity error sources.
Starting Page	242
Ending Page	246
File Size	240163
Page Count	5
File Format	PDF
ISBN	9781424473212
e-ISBN	9781424473205
DOI	10.1109/ISVLSI.2010.27
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Pipelines Solid state circuits CMOS integrated circuits Linearity Mathematical model Equations Integer Division Analog Digital Converters
Content Type	Text
Resource Type	Article

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