NDLI: Hybrid QoS Method for Networks-on-Chip

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Table of Contents

Message from General Chairs

Program Committee

European ICT Research: 2011-2012 Outlook for Components and Systems

Digital Microfluidic Biochips: A Vision for Functional Diversity and More Than Moore

Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture

Reconfigurable Architectures for Bioinformatics Applications

Challenges and Perspectives of Computer Architecture at the Nano Scale

SUT-RNS Forward and Reverse Converters

Clock Tree Synthesis with XOR Gates for Polarity Assignment

A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells

A BDD-Based Design of an Area-Power Efficient Asynchronous Adder

Efficient Hardware Looping Units for FPGAs

Exploration of 2D Cellular Automata as Binary Sequence Generators

Fine-Grained Fault Tolerance for Process Variation-Aware Caches

Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA

Self-Freeze Linear Decompressors for Low Power Testing

Logical Core Algorithm: Improving Global Placement

Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder

Input-Output Selection Based Router for Networks-on-Chip

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching

Adaptive Task Migration Policies for Thermal Control in MPSoCs

A Scalable Bandwidth Aware Architecture for Connected Component Labeling

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest

Differential Power Analysis of CAST-128

QCA Systolic Matrix Multiplier

Hardware Module Design for Ensuring Trust

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform

Task Dispersal Measurement in Dynamic Reconfigurable NoCs

Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars

ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital Converters

A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration

A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity

Memory-Less Pipeline Dynamic Circuit Design Technique

A Floating Gate MOSFET Based Current Reference with Subtraction Technique

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

Pattern-Driven Clock Tree Routing with Via Minimization

Ultra-Low-Power Sensor Signal Monitoring and Impulse Radio Architecture for Biomedical Applications

Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs

Testing Parametric and Catastrophic Faults in Mixed-Signal Integrated Circuits Using Wavelets

A Receiver Circuit for Low-Swing Interconnect Schemes

An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division

DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation

Fast Evaluation of Analog Circuits Using Linear Programming

FGMOS Based Built-In Current Sensor for Low Supply Voltage Analog and Mixed-Signal Circuits Testing

A Sub-1μA Low-Power FSK Modulator for Biomedical Sensor Circuits

Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology

Low Power Single Electron Or/Nor Gate Operating at 10GHz

Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material

A Mesh-Buffer Displacement Optimization Strategy

BLAS Comparison on FPGA, CPU and GPU

Novel Architecture for Highly Hardware Efficient Implementation of Real Time Matrix Inversion Using Gauss Jordan Technique

Reliability Analysis and Improvement in Nano Scale Design

Reliability-Aware Dynamic Voltage and Frequency Scaling

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array

A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network

Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology

A Hierarchical Hybrid Optical-Electronic Network-on-Chip

A High Throughput Low Power FIFO Used for GALS NoC Buffers

An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs

A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio

Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture

Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model

An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-Chip

Hybrid QoS Method for Networks-on-Chip

XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation

Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and Repair

A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface

Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays

A New Low-Power Soft-Error Tolerant SRAM Cell

The Impact of Process Faults on Specific Parameters of a 1.9GHz CMOS Mixer

Improved Yield in Nanotechnology Circuits Using Non-square Meshes

Dynamic Power Management on LDPC Decoders

Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture

Bitstream Efficiency of Field Programmable One-Hot Arrays

A Family of Area-Time Efficient Modulo 2n+1 Adders

A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd

Towards Supporting Fault-Tolerance in FPGAs

Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead

A Novel On-Chip Interconnection Topology for Mesh-Connected Processor Arrays

BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters

A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics

Side Channel Attacks Cryptanalysis against Block Ciphers Based on FPGA Devices

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique

Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform

High-Performance TSV Architecture for 3-D ICs

Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA

Design Automation and Analysis of Resonant Rotary Clocking Technology

System Level Design of Complex Hardware Applications Using ImpulseC

Two-Dimensional Dynamic Multigrained Reconfigurable Hardware

FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications

Performance Analysis of 3D NoCs Partitioning Methods

Autonomous Design in VLSI: Growing and Learning on Silicon

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures

System Level Design for Embedded Reconfigurable Systems Using MORPHEUS Platform

The SATURN Approach to SysML-Based HW/SW Codesign

Mapping Embedded Applications on MPSoCs: The MNEMEE Approach

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

Publisher's Information

2009 IEEE Computer Society Annual Symposium on VLSI

2008 IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

Hybrid QoS Method for Networks-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Shijun Lin Jianghong Shi Huihuang Chen
Copyright Year	2010
Abstract	In this paper, we propose a hybrid method to provide Quality of Service (QoS) for Networks-on-Chip (NoC). This method combines the advantages of connection-based schemes and connection-less schemes. Thus, compared with traditional methods, this method guarantees the latency between one flit’s generation in the source node and its reception in the destination node, supports a wide range of traffic types such as latency critical, low bandwidth traffic and streaming data which only have bandwidth requirement, and has high link-bandwidth utilization. Moreover, the NoC which supports the proposed method is implemented. Simulation and synthesis results show that this method can guarantee the bandwidth and latency well and is relatively low-cost.
Starting Page	369
Ending Page	374
File Size	360605
Page Count	6
File Format	PDF
ISBN	9781424473212
e-ISBN	9781424473205
DOI	10.1109/ISVLSI.2010.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	IP networks Bandwidth Nickel Quality of service Buffer storage Switches System-on-a-chip Quality of Service Network-on-Chip System-on-Chip
Content Type	Text
Resource Type	Article

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