NDLI: Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration

Content Provider	IEEE Xplore Digital Library
Author	Hübner, M. Meyer, J. Sander, O. Braun, L. Becker, J. Noguera, J. Stewart, R.
Copyright Year	2010
Abstract	Due to their their high flexibility and their increasing logic resources, FPGAs can be found in a wider application range as in recent years. But especially in application domains, where only a very restricted power budget is available, FPGAs still have to compete with other solutions. To reduce the power consumption to a minimum, many devices use different kinds of power saving modes, called sleep modes. In those modes they sacrifice functionality for the benefit of a lower consumption. Taking this idea to the extreme, many devices are only powered when it is necessary. If not, they are released from their power supply and do not drain current at all. The realization of such a sleep mode for a SRAM-based FPGA leads to difficulties. This is caused due to the fact, that the volatile memory is used to save the configuration of the device. The configuration has to be reloaded into the device every time when reattaching the power to the FPGA. This circumstance leads to restrictions for the device deployment in some electronic systems since in many cases the time a device may use to wake up is strictly limited. In several use cases, the configuration time of a SRAM based FPGA exceeds this limitation. This paper describes to decrease the configuration time of a design by exploiting the method of dynamic and partial reconfiguration in order to enable the usage of a sleep mode. With the presented method, the configuration time of any Xilinx SRAM based FPGA from the identical series (e.g. Spartan) is independent from the size of the used device.
Starting Page	190
Ending Page	194
File Size	535572
Page Count	5
File Format	PDF
ISBN	9781424473212
e-ISBN	9781424473205
DOI	10.1109/ISVLSI.2010.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Vehicle dynamics Hardware Clocks Microprocessors SRAM based FPGA Dynamic and partial reconfiguration fast wakeup
Content Type	Text
Resource Type	Article

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