NDLI: A new asymmetric skewed buffer design for runtime leakage power reduction

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A new asymmetric skewed buffer design for runtime leakage power reduction

Content Provider	IEEE Xplore Digital Library
Author	Yu-Shiang Lin Sylvester, D.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA (Yu-Shiang Lin; Sylvester, D.)
Abstract	A novel asymmetric skewed buffer is proposed to reduce the subthreshold leakage of standard CMOS noninverting buffers. Using oppositely skewed inverters to drive the NMOS and PMOS of the second inverter creates a small time window during which both transistors are conducting, enhancing speed. Given this performance advantage over traditional CMOS buffers, the leakage current can then be suppressed by either downsizing transistors or by assigning high-Vt devices. Based on simulation results for a 0.13 /spl mu/m technology, leakage is reduced by up to 4.4 times when the input is high while maintaining fixed dynamic power dissipation and propagation delay compared to CMOS.
Starting Page	824
Ending Page	827
File Size	136595
Page Count	4
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.23
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime MOS devices Threshold voltage Inverters Switches Transistors Degradation Delay Subthreshold current Leakage current
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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