NDLI: On physical-aware synthesis of vertically integrated 3D systems

Content Provider	IEEE Xplore Digital Library
Author	Mukherjee, M. Vemuri, R.
Copyright Year	2005
Description	Author affiliation: Dept. of ECECS, Cincinnati Univ., OH, USA (Mukherjee, M.; Vemuri, R.)
Abstract	Vertical integration of active device layers in the third dimension makes room for significant reduction in interconnect lengths leading to decrease in both delay and power consumption associated with interconnects. This characteristic can be well leveraged only by judicious layer assignment of active devices. To address layer assignment as a part of behavioral synthesis, we proposed a 0-1 linear program formulation to simultaneously schedule, bind and perform layer assignment for synthesis of vertically integrated 3D systems. In these systems, inter-stratal communication occurs through inter-layer vias that have higher resistivity and capacitance. In this paper, we propose a trade-off between reducing the total interconnect delay in critical paths while reducing the inter-stratal communication. Three different objective models are proposed and their combinations examined to find the most suitable methodology to achieve these goals. A power gradient is proposed between layers to address the thermal issues associated with these systems that have been shown to be of concern. Results shows a significant reduction in total interconnect lengths compared to a traditional two-dimensional implementation. The examination of the various proposed optimization objectives indicate that a combination of communication minimization and critical path optimization leads to the best synthesis results for a range of benchmarks.
Starting Page	647
Ending Page	652
File Size	159274
Page Count	6
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Power system interconnection High level synthesis Delay Temperature Power dissipation Logic Thermal resistance Energy consumption Conductivity
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in