NDLI: Formal methods for analyzing the completeness of an assertion suite against a high-level fault model

Content Provider	IEEE Xplore Digital Library
Author	Sayanlan Das Ansuman Banerjee Basu, Prasenjit Dasgupta, Pallab Chakrabarti, P.P. Chunduri Rama Mohan Fix, L.
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India (Sayanlan Das; Ansuman Banerjee; Prasenjit Basu; Pallab Dasgupta; Chakrabarti, P.P.)
Abstract	One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design intent. Existing literature on FPV coverage does not solve this problem adequately, since they primarily analyze the coverage of a specification against a given implementation. On the other hand, we consider the task of determining the coverage of a formal specification against a high-level fault model that is independent of any specific implementation. We show that such a coverage analysis discovers behavioral gaps in the specification and prompts the design architect to add more properties to close the behavioral gaps. Our results establish that the coverage analysis task at this level is computationally complex, but it is possible to obtain a conservative estimate of the coverage at low cost.
Starting Page	201
Ending Page	206
File Size	131557
Page Count	6
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.101
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Formal specifications Computer science Strategic planning Logic design Costs Computational modeling Testing Writing Standards development
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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