NDLI: Integrated on-chip storage evaluation in ASIP synthesis

Content Provider	IEEE Xplore Digital Library
Author	Manoj Kumar Jain Balakrishnan, M. Anshul Kumar
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India (Manoj Kumar Jain; Balakrishnan, M.; Anshul Kumar)
Abstract	An application specific instruction set processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements. Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by approaches which perform only scheduling for performance estimation and avoid code generation. However, existing scheduler based approaches do not help in exploring on-chip storage organization. We present a scheduler based technique for exploring the register file size, number of register windows and cache configurations in an integrated manner. Performance for different register file sizes are estimated by predicting the number of memory spills and its delay. The technique employed does not require explicit register assignment. Number of context switches leading to spills are estimated for evaluating the time penalty due to a limited number of register windows and cache simulator is used for estimating cache performance.
Starting Page	274
Ending Page	279
File Size	162205
Page Count	6
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific processors Registers Processor scheduling Space exploration Costs Aerospace electronics Space technology Application software Delay estimation Control systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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