NDLI: Energy-efficient compressed address transmission

Content Provider	IEEE Xplore Digital Library
Author	Jiangjiang Liu Sundaresan, K. Mahapatra, N.R.
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci., Lamar Univ., Beaumont, TX, USA (Jiangjiang Liu)
Abstract	To realize energy-efficient buses in current nanometer-scale technologies, techniques like compression or encoding that exploit information redundancy have been explored. However, available compression techniques for buses do not always ensure energy-efficient transmission of compressed information. In this work, we present various techniques that can be used with compression schemes for buses to ensure high energy efficiency. Our best scheme, applied to a stream of 38-bit addresses issued in a typical microprocessor, yields about 14.7% energy reduction on the average across a wide range of compressed bus widths ranging and over many SPEC CPU2000 benchmarks. Our proposed techniques especially perform better - up to 28.8% energy reduction is obtained - for narrower bus widths in the range 8-16 bits.
Starting Page	592
Ending Page	597
File Size	154296
Page Count	6
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.91
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Encoding Electronic mail Microprocessors Costs Computer science Power engineering and energy Statistics Capacitance Wires
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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