NDLI: Test methodologies in the deep submicron era

Content Provider	IEEE Xplore Digital Library
Author	Chatterjee, A. Keshavarzi, A. Patra, A. Mukhopadhyay, S.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Chatterjee, A.)
Abstract	Summary form only given. The goal of this tutorial is to give the audience a detailed overview of testing challenges, proposed solutions and open problems. The tutorial starts with the introduction to testing challenges in the deep sub micron era. Issues with process variations and leakage and their impact on testing are discussed. This is followed by issues regarding fault modeling, DFT and BIST of analog and mixed signal circuits. It is shown how behavioral modeling could be utilized for such circuits in, conceptually, the same way that stuck-at fault modeling is used for digital testing. Issues and conceptual details regarding on-line testing are introduced, both in the contexts of digital as well as mixed signal circuits. The last part of the tutorial introduces in detail concept of built-in test (BIT) and built-off self-test (BOST) for high frequency RF circuits. A new paradigm for BIST of high-speed/RF circuits using alternate tests is also introduced.
Starting Page	12
Ending Page	13
File Size	40245
Page Count	2
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.161
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency Circuit testing Automatic testing Built-in self-test System testing Circuit faults Very large scale integration Microprocessors Laboratories Electronic equipment testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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